Terminology

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CRC:

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To an observer, the data on a live T1 Circuit appear to be random. Fortunately there is a way to perform limited testing when the circuit is designed for Extended Super Frame (ESF) format. A portion of the frame bits are reserved for a Cyclic Redundancy Checksum (CRC) sequence that can be monitored for performance. Simply stated, the CRC bits are calculated on the transmit end and inserted as a pattern on the frame bit. The CRC pattern depends on the pattern of other bits transmitted by the T1 Circuit. The receiving end also computes this pattern and compares it with the CRC that was computed and sent by the transmitting end. Since both ends use the same rules for computing the pattern, the CRC bits will be identical when all the bits involved in the computation agree. The CRC check provides good insight into the end-to-end integrity of the T1 Circuit and should be used in conjunction with other tests that can help determine what the cause of the CRC failure might be.